Guest lecture: High Level Synthesis of Hardware and Software for Customized Computing

Dr. Konstantinos Masselos, Department of Informatics and Telecommunications, University of Peloponnese, Greece.

04.01.2017 | Jens Kargaard Madsen

Dato tor 12 jan
Tid 13:00 14:00
Sted Room 235E, building 5125, Finlandsgade 22, 8200 Aarhus N

It has long been observed that human designers’ productivity in computer systems development does not escalate sufficiently enough to match the corresponding increase in application complexity and technology capabilities. Notably, the annual increase of chip complexity is 58%, while human designers’ productivity increase is limited to 21%. A dramatic increase in designer productivity is only possible through the adoption and practicing of methodologies that raise the specification abstraction level, ingeniously hiding low-level, time-consuming, error-prone details. In this context there is need for design automation in the form of compilers generating implementation code (e.g. C or VHDL etc) from higher level code both for customized hardware and software implementations. In this talk, we provide introduction of two high level synthesis tools for computer systems development. To that end, we first consider MAFE MATLAB vectorizing compiler that exploits custom instructions present in state-of-the-art processors and in Application Specific Instruction Set Processors (ASIPs) and generates optimized C code from MATLAB sources. Τhe specialized instruction set of the target processor is described in a parameterized way using a target processor independent architecture description allowing the support of any processor. Then we consider HercuLeS high level synthesis tool that automatically generates customised hardware as extended finite-state machines with datapath (FSMD) in VHDL. Essentially, HercuLeS translates programs in the N Address Code (NAC) Intermediate Representation to a collection of Graphviz control-data flow graphs (CDFGs) which are then synthesised to vendor-independent self-contained RTL VHDL.

Konstantinos Masselos received a first degree in Electrical Engineering from University of Patras, Greece in 1994 and an MSc in VLSI Systems Engineering from University of Manchester Institute of Science and Technology, United Kingdom in 1996. In April 2000 he received a PhD in Electrical and Computer Engineering from University of Patras, Greece in cooperation with the Inter-university Micro Electronics Centre (IMEC) in Belgium where he was a researcher from 1997 - 1999. In 2001 he joined Intracom S.A, Greece where he was involved in R&D projects for the development of wireless communication systems. In 2005 he joined the Department of Electrical and Electronic Engineering of Imperial College London as a Lecturer in Digital Systems. Since 2006 he is with University of Peloponnese where he is currently a Professor in the Department of Informatics and Telecommunications and Director of the Computer Systems laboratory. Since 2006 he is associated with the Department of Electrical and Electronic Engineering of Imperial College London as a part time lecturer/honorary lecturer. His main research interests include compilers and high level synthesis, FPGAs and integrated circuits design and low power design. He has authored more than 100 papers in international journals and conferences. Since 2005 he is also regularly involved as an expert with different European Commission units. Since 2013 he is the Rector of the University of the Peloponnese.

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